Non-volatile data storage devices, such as embedded flash memory, have allowed for increased portability of data and software applications. Information that is read from a non-volatile data storage device is often processed by an error correction code (ECC) decoder to correct errors that may be introduced into stored data during operation of the non-volatile data storage device. One example of such an ECC decoder is a low-density parity check (LDPC) decoder. Another example is a bit-flipping ECC decoder. The bit-flipping ECC decoder is faster and uses less power than most belief propagation (BP) LDPC decoders, and thus the bit-flipping decoder is often used as a first “gear” of a “multi-gear” ECC decoder. In many situations, the bit error rate (BER) of a representation of data read from a memory is sufficiently small that a bit-flipping ECC decoder is able to decode the representation of data without using more powerful decoders, such as a BP LDPC decoder.
The bit-flipping ECC decoder may use a single set of thresholds when determining whether to “flip” a particular bit (e.g., to set a bit having a logical “0” value to a logical “1” value or to set a bit having a logical “1” value to a logical “0” value) during a decoding process. The single set of thresholds is based on a fixed model of a channel (e.g., between a controller and the memory). However, as memory fabrication processes decrease in size and as three-dimensional (3D) stacking of memory dies becomes more common, variance within memory dies, blocks, or pages increases. The increasing variability results in errors associated with some dies, blocks, or pages diverging from a single underlying model. This divergence can reduce correction capability and increase latency and power consumption of a bit-flipping ECC decoder.